Job details
Job type full-time
Full job description
Cyient is a global engineering and technology solutions companyAs a design, build, and maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curveWe leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.
With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization’s culture and requirementsOur industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.
Job description
Ibm, in support of a u.s government customer, has a need for a very experienced and growth minded mission engineerThis engineer will be responsible for system verilog verification in a cadence environment.this effort will primarily focus on the writing of tests for individual components of the chip in a progressive sequence based on the functional description provided in the chip specification
Workscope includes test creation, setup, run and debug of verilog simulations in a cadenceincisive/xcelium environment,the ability to read/edit standard verilog models (ie debug issues), the ability to assemble of chip design modules into a top-level chip and the ability to read/write tlc scripts.prior experience with asic chip design using the cadence design environment, an intimate knowledge/use of scripting languages such as tcl.
The selected candidate will be required to work both independently and collaboratively in conjunction with other teams across ibm.as such, the ability to be a hands-on person is critical, capable of running tools, while working effectively with others, while having the willingness and ability to learn new tools.
Task description:
Job duty 1 write/code verification tests based on the chip specification.
Job duty 2s etup, run, and debug verilog simulations in a cadence environment (i.eIncisive/xcelium).
Job duty 3 debug verilog
Required skills/level of experience :
Asic design engineer - verilog simulation – electrical / computer engineer
At least 10-15 years of experience.experience with assembly language coding, writing in c and with the debugging of complex processor logic is essential.
Work to be performed at:
Street address:
Ibm yorktown or remotely
City, state:
Yorktown, ny
Skills & experience
Application specific integrated circuits (asic), digital verification, system verilog, uvm
Cyient is an equal opportunity employer.
Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable lawWe are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.
