Job details
Job type full-time
Full job description
Position title: rtl design engineer
Location: 100% remote
Full-time: salary + benefits + bonuses
About the project:
As a senior member of the development team, you will develop microarchitecture and rtl code based on architecture definitions for a wide variety of soc or asic based applicationsThese projects involve development of logic functions as well as integration of standard ips and interfaces and provide opportunities to contribute at both the detailed block level and with top-level integrationOnce created, you will work with verification engineers to ensure the designs are functionally correct as well as with physical design engineers to enable synthesis and timing closure to enable the tape-out of the overall designIf you have a background in logic development and rtl coding, joining the encore semi front-end development team could be for you.
Minimum qualifications:
Rtl coding experience in verilog and systemverilog
Experience working with verification and physical design engineers to iterate on your design to deliver functionally correct and synthesizable rtl
Hands-on experience with lint, clock domain crossing, synthesis and timing constraints generation
Bsee with 7+ years of experience in logic design and chip integration
Preferred qualifications:
Rtl and logic design at both the ip / unit as well as the “full-chip” / soc levels and the ability to easy move from one to the other
Experience designing with either internal interfaces (such as arm interconnects like axi or proprietary interconnects) or external interfaces (such as pcie, usb, srio, etc)
