Job details
Job type full-time number of hires for this role 1
Qualifications
Specify and drive ip requirements in the physical domain: 1 year (preferred)
Full job description
Design and implementation of high-performance, low-power fpga socs, including integration of analog and digital ips from both internal and external vendors.
Write rtl design and debug of complex blocks in verilog / system verilog.
Analyze design and make implementation choices to optimize timing and power.
Work with verification and physical design teams to achieve high quality design and successful tape-out.
Minimum qualifications:
Minimum bsc in cs/ce/ee or equivalent and 4 years of experience
Asic design flow and direct experience with asic design in sub-28nm technology nodes
Experience in integrating ip from both internal and external vendors and the ability to specify and drive ip requirements in the physical domain.
Experience with large soc designs ( >20m gates) with frequencies in excess of 1ghz utilizing state of the art sub 45nm technologies.
Detailed understanding of database management issues
From a cad tool perspective, experience with floor planning tools, p&r flows, global timing verification and physical design verification flows
Familiarity with various process related design issues including design for yield and manufacturability, multi-vt strategies and thermal management
Understanding of fpga architecture and implementation is a plus
Job type: full-time
Benefits:
Dental insurance
Health insurance
Paid time off
Vision insurance
Experience:
Integrating ip from both internal and external vendors: 1 year (preferred)
Specify and drive ip requirements in the physical domain: 1 year (preferred)
Work location:
One location
Work remotely:
Yes
Work location: one location
